integrated circuit systems, inc. general description features av9 172 block diagram av9172revb060297p the av9172 is designed to generate low skew clocks for clock distribution in high-performance pcs and workstations. it uses phase-locked loop technology to align the phase and frequency of the output clocks with an input reference clock. because the input to output skew is guaranteed to 500ps, the part acts as a zero delay buffer. the av9172 has six configurable outputs. the av9172-01 version has one output that runs at the same phase and frequency as the reference clock. a second output runs at the same frequency as the reference, but can either be in phase or 180 out of phase from the input clock. two outputs are provided that are at twice the reference frequency and in phase with the reference clock. the final outputs can be programmed to be replicas of the 2x clocks or non-overlapping two phase clocks at twice the reference frequency. the av9172-01 and av9172-03 operates with input clocks from 10 mhz to 50 mhz while producing outputs from 10 mhz to 100 mhz. the av9172-07 operates with input clocks from 20 to 100 mhz. the use of a phase-locked loop (pll) allows the output clocks to run at multiples of the input clock. this permits routing of a lower speed clock and local generation of a required high speed clock. synchronization of the phase relationship between the input clock and the output clocks is accomplished when one output clock is connected to the input pin fbin. the pll circuitry matches rising edges of the input clock and output clocks. ? av9172-07 input is 66 mhz with 66 and 33 mhz output buffers ? av9172-01 is pin compatible with gazelle ga1210e ? 250ps skew (max) between outputs ? 500ps skew (max) between input and outputs ? input frequency range from 10 mhz to 50 mhz (-01, -03) and from 20 mhz to 100 mhz (-07) ? output frequency range from 10 mhz to 100 mhz (-01, -03, -07) ? special mode for two-phase clock generation ? inputs and outputs are fully ttl-compatible ? cmos process results in low power supply current ? high drive, 25ma outputs ? low cost ? 16-pin soic (150-mil) or 16-pin pdip package low skew output buffer the av9172 is fabricated using cmos technology which results in much lower power consumption and cost compared with the gallium arsenide-based ga1210e. the typical operating current for the av9172 is 50ma versus 120ma for the ga1210e. ics offers several versions of the av9172 . the different devices are shown below: part description av9172-01 second source of ga1210e av9172-03 clock doubler and buffer av9172-07 clock buffer for 66 mhz input ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 av9172 pin configuration pin description for av9172-01 16-pin soic or 16-pin pdip functionality table for a v9172-01 clkin input frequency range 10 to 50 mhz. notes: 1. 1x designates that the output is a replica of clkin. 2. 2x designates that the output is twice the frequency of clkin, and in phase. 3. 1x# means that the output is at the same frequency and 180c out of phase (inverted) from clkin. 4. ?1 will produce a ? duty cycle clock of clkin. 5. ?2 will produce a ? duty cycle clock delayed 180 from clkin. en2 inv# q0 q1 q2 q3 q4 q5 0 0 1x 1x# 2x 2x 2x 2x 0 1 1x 1x 2x 2x 2x 2x 1 0 1x 1x# 2x 2x ? 1 ? 2 1 1 1x 1x 2x 2x ? 1 ? 2 pin number pin name type description 1 gnd - ground. 2 gnd - ground. 3 inv# input inv# inverts q1 when low. (-01 [divisor select -03, -07]) 4 en input en converts q4 and q5 to phase clocks when high. 5 fbin input feedback input from output q0. 6 clkin input input for reference clock. 7 vdd - power supply (+5v). 8 vdd - power supply (+5v). 9 gnd - ground. 10 q0 output q0 phase and frequency same as input (1x). feed back to pin 5. 11 q1 output q1 is a 1x clock in phase or 180 out of phase with input. 12 q2 output q2 twice the frequency of q0 (2x). 13 q3 output q3 twice the frequency of q0 (2x). 14 q4 output q4 is either a 2x clock or a two-phase clock - see configuration table. 15 q5 output q5 is either a 2x clock or a two-phase clock - see configuration table. 16 vdd - power supply (+5v).
3 av9172 timing diagrams for av9172-01
4 av9172 pin configuration functionality table for a v9172-03 clkin input frequency=x, input range is 10 to 50 mhz. example table for av9172-03 (33 mhz input, all frequencies in mhz.) timing diagram for av9172-03 16-pin soic or 16-pin pdip note: the phase alignment between the 1x clock outputs and reference clocks input will be either at a 0 or 180 degrees offset if the 2x clock is used as the feedback signal (con- nected to the fbin pin). which relationship occurs is totally random and has the potential to change any time the device has its vdd supply cycled off or the devices input clock removed. en2 inv# q0 q1 q2 q3 q4 q5 0 0 2x 2x 2x 2x 2x 2x 1 0 2x 2x 2x 2x 2x 1x 0 1 2x 2x 2x 1x 1x 2x 1 1 2x 2x 2x 1x 1x 1x en2 inv# q0 q1 q2 q3 q4 q5 0 0 66 66 66 66 66 66 1 0 66 66 66 66 66 33 0 1 66 66 66 33 33 66 1 1 66 66 66 33 33 33
5 av9172 absolute maximum ratings vdd referenced to gnd . . . . . . . . . . . . . . . . . . . . . . 7v operating temperature under bias. . . . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c voltage on i/o pins referenced to gnd. . . . . . . . . . . gnd -0.5v to vdd +0.5v power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 watts stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. pin configuration functionality table for a v9172-07 clkin input frequency=x, input range is 20 to 100 mhz. example table for av9172-07 (66 mhz input, all frequencies in mhz.) 16-pin soic or 16-pin pdip timing diagram for av9172-07 en2 inv# q0 q1 q2 q3 q4 q5 0 0 1x 1x 1x 1x 1x 1x 1 0 1x 1x 1x 1x 1x 0.5x 0 1 1x 1x 1x 0.5x 0.5x 1x 1 1 1x 1x 1x 0.5x 0.5x 0.5x en2 inv# q0 q1 q2 q3 q4 q5 0 0 66 66 66 66 66 66 1 0 66 66 66 66 66 33 0 1 66 66 66 33 33 66 1 1 66 66 66 33 33 33
6 av9172 electrical characteristics v dd =+5v5%, t a =0c to 70c unless otherwise stated *parameter guaranteed by design and characterization. not 100% tested in production. notes: 1. output frequency includes both the fast clock (2x or 1x) and the slow clock (1x or 0.5x) extremes. 2. all skew specifications are measured with a 50w transmission line, load terminated with 50w to 1.4v. 3. duty cycle measured at 1.4v. 4. skew measured at 1.4v on rising edges. loading must be equal on outputs. dc characteristics parameter symbol test conditions min typ max units input low voltage v il v dd =5v - - 0.8 v input high voltage v ih v dd =5v 2.0 - - v input low current i il v in =0v -5 - 5 a input high current i ih v in =v -5 - 5 a output low voltage v ol *i ol =25ma - 0.5 0.8 v output high voltage v oh *i oh =-25ma 2.4 - - v supply current i dd unloaded, 50 mhz outputs - 35 60 ma ac characteristics input clock rise time iclk r *--10ns input clock fall time iclk f *--10ns output rise time, 0.8 to 2.0v t r * 15pf load - 0.7 1 ns rise time, 20% to 80% v dd t r * 15pf load - 1.2 2 ns output fall time, 2.0 to 0.8v t f * 15pf load - 0.7 1 ns fall time, 80% to 20% v dd t f * 15pf load - 1.2 2 ns output duty cycle d t * 15pf load 45 49/51 55 % jitter, 1 sigma t 1s *60ps jitter, absolute t abs * ae200 ps input frequency (-01,-03) f i * 10 50 mhz input frequency (-07) f i * 20 100 mhz output frequency (-01,-03, -07) f o * note 1 10 100 mhz fbin to in skew t skew1 * note 2, 4. input rise time < 3ns -500 -300 500 ps fbin to in skew t skew1 * note 2, 4. input rise time < 10ns 1000 -500 1000 ps skew between any 2 outputs at same frequency t skew2 * note 2, 4 -250 50 250 ps skew between any 2 outputs at different frequencies note 2, 4 500 ps
7 av9172 typical performance characteristics
8 av9172 ordering information ics xxxx-ppp m x#w pattern number (2 or 3 digit number for parts with rom code patterns) device type (consists of 3 or 4 digit numbers) prefix ics, av=standard device example: 16-pin pdip package 16-pin soic package part number part marking temperature package type av9172-xxcc16 av9172-xx 0c to 70c 16 lead cerdip av9172-xxcn16 av9172-xx 0c to 70c 16 lead plastic dip (300 mil) av9172-xxcw16 av9172-xx 0c to 70c 16 lead soic (300 mil) av9172-xxcs16 av9172-xx 0c to 70c 16 lead soic (150 mil) lead count & package width lead count=1, 2 or 3 digits w=.3 soic or .6 dip; none=standard width package type c= cerdip n=dip (plastic#) w=soic (300 mil) s=soic (150 mil) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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